Via in Pads, considerations, stress,…

Via in Pad, considerations, stress,…

In PCB design, via refers to a pad with a plated hole that connects copper tracks from one layer of the board to other layer(s). High Density Multilayer PCBs may have what is normally referred to as micro vias micro used as blind vias, which are visible only on one surface, or buried vias, which are visible on neither The advent and extensive use of finer pitch devices and requirements for smaller size PCBs creates new challenges. An exciting solution to these challenges uses a recent, but common PCB manufacturing technology with self-descriptive name, “Via In Pad”.


Via In Pad helps to reduce inductance, increase density and manage us to use finer pitch array packages. The Via In Pad approach places vias directly under the device’s contact pads. This allows higher component density and improved routing. Consequently, via in pad provides the designer significant PCB space savings.

Filled via in pad is a way to achieve intermediate density with an intermediate cost compared to using blind/buried vias. Some of the key advantages associated with using the via in pad technology are:

   Fan out fine pitch (less than .75mm) BGAs

   Meets closely packed placement requirements

   Better thermal management

   Overcomes high speed design issues and constraints, e.g. low inductance

   No via plugging is required at component locations

   Gives a flat, coplanar surface for component placement 

Both stacked- and staggered- vias can be delivered from Elmatica approved manufacturers in Europe, US and the East.

However, there are some disadvantages associated with this technology, and that is the cost impact associated with adopting a new technology. PCB manufacturers identified two primary cost drivers associated with specifying Via In Pad technology: Additional manufacturing process complexity and the underlying material cost for the conductive fill.

Via In Pad technology will add up to 10 steps to the board manufacturing process while via fill cost is a function of the via size and actual number of via instances on any given design. However, the reduction in layer count realized by using Via In Pad technology can compensate for the added cost associated with this process.

Another issue that must be considered when using Via In Pad: Shall we use stacked or staggered vias? When using staggered vias, there will normally be only one via level from a SMD pad and down to first level. But when using stacked vias there can be vias in 2-4 (even more) levels. 3-stacked vias on top of each other will reach through 4 layers in the PCB. They are all “metallized” and the total metallization will be quite heavy compared to the solderpad. During soldering, heat dissipation will be much more dominant compared to the solderpads with a staggered via or no via at all. Both via types can also be placed on top of a RFP (Resin Filled PTH (Plated Through Hole)). Another aspect is the stress factor in z-axis in the cases where several vias are stacked. Increasing the number of vias in the stack, the maximum stress in the stack will become bigger.

Both stacked- and staggered- vias can you get from Elmatics manufacturers in both Europe and Fare East.

This opens a new dimension to  the DFM channel. Assembly houses must know even more about the design and how the specific boards are designed, so the correct soldering parameters for components / areas of the boards can be established.


See .pdf file for full article with illustrations..   


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