Controlled Impedance Designs


Controlled Impedance Designs            



In today’s world of high-speed digital systems with clock edge rates commonly approaching 10 Gbps and analog frequencies above the 5-10 GHz range, copper trace interconnects on printed circuit boards (PCBs) must be considered as transmission lines. Transmission lines are electronic interconnects that distribute high-speed digital signals over copper media, and these lines must be controlled by the PCB designer.

The critical parameter is the characteristic impedance of the PCB trace, which is the ratio of a voltage to the current of a waveform moving along the trace.
This voltage to current ratio is a function of frequency and a function of the physical geometries of the transmission line and its relationship to surrounding dielectric properties.



Electrical components possess certain characteristic impedance values, which will vary depending on the logic family. The designer’s responsibility is to match the impedance of the component’s load and source requirements with that of the interconnecting PCB traces.
To achieve maximum signal transfer from a source (sending unit) to a load (receiving unit), the PCB trace impedance must match the output impedance of the source to the input or load.
If the impedance of the PCB trace connecting two components does not match the components’ characteristic impedance, multiple waveform reflections will occur on the signal line before the load device can settle into a new logic state.
This will result in increased switching times within the device or the circuit and produce random errors. The circuit design engineer and PCB designer must carefully select a nominal value and tolerance of trace impedance. Tolerances of 10% or less are not uncommon for high-speed applications.



The characteristic impedance of a PCB trace is typically determined by its inductive and capacitive reactance, resistance, and conductance. These parameters will be a function of the physical dimensions of the trace, the dielectric constant of the PCB substrate material, and dielectric thickness. PCB trace impedance can range from
25 to 120 ohms.
PCB transmission lines consist of a copper trace conductor, reference copper ground or power plane layers, and dielectric substrate. The relationship between the copper trace conductor layers and the reference plane layers (where the signal return path flows) form the controlled impedance structure and because of this structure, most controlled impedance PCBs will be multilayer structures.

The impedance value generated from the PCB structure will be determined by the following parameters:

     - width and thickness of the copper signal trace
     - thickness of the core or prepreg material on either side of the copper trace
     - dielectric constant of the core and prepreg material



Single-ended transmission lines are the most common way to connect two devices. This case is where a single conductor or PCB trace connects the source of one component to the load of another. There must be a reference or ground plane on the adjacent layer in order to provide a signal return path. Controlled impedance designs are usually produced with microstrip, embedded microstrip, stripline, or dual asymmetrical stripline configurations.

Differential configurations of transmission lines are used when better noise immunity and improved timing are required in critical applications. Typical configurations will have a balanced line where the signal and return paths have similar geometry. There are two modes of differential configuration: even and odd mode.

Even mode is where the same signal is sent through both lines and there is no return path.
For this configuration, the electrical field lines are directed toward ground with no coupling to each other.
Odd mode is where the signals are sent in a complementary form and the signals are actually mirrored so that the voltage and current flows are opposite. The electrical fields are coupled together along the surface between the two adjacent signals. With the voltage reversed, the electric fields will originate with one line and terminate with the other.
This is the differential form of signal transmission and results in good coupling.

Surface microstrip configurations are designed on the outer layers of the PCB. The external trace is referenced to the adjacent internal plane layer. The width and thickness of the trace are difficult to control due to plating current density

variations at panel plate and copper etch variations These plating and etch differences can cause significant impedance variations. Typically there is a soldermask layer applied over the traces.

Embedded microstrip configurations are similar to surface microstrips but will have an additional layer of laminate over the microstrip trace and may have soldermask over the laminate. This configuration references a single internal plane layer and is much more predictable due to the lack of copper plating.

Stripline configurations are designed on the internal layers of the PCB with a single trace centered between adjacent reference plane layers. Due to the symmetry of the trace in the z-axis, there is enhanced predictability. This configuration is

the most immune to crosstalk and EMI because of the adjacent plane layers. The use of this configuration will increase the number of layers in the PCB and typically increase overall board thickness per layer.


Asymmetrical stripline configurations are designed on internal layers of the PCB similar to stripline. However, there are two trace layers separated by a layer of laminate material and centered between two adjacent plane layers. This configuration has each trace layer referencing two planes, provides for low impedance variation, and will help reduce board thickness per signal layer. To aid in noise immunity and minimize crosstalk with this configuration, a routing bias of horizontal and vertical traces should be used.



Impedance measurements are usually made with a Time Domain Reflectometer or TDR. The TDR applies a fast voltage step to the coupon through a controlled impedance cable and probe. Any reflections in the pulse waveform are displayed on the TDR and indicate a change in impedance value (this is known as a discontinuity). The TDR is able to indicate the location and scale of discontinuity.




The performance of a PCB with controlled impedance circuitry is directly dependent on the accuracy of the controlled impedance traces and their reference coupon. Since the accuracy of the controlled impedance trace is dependent on a number of factors including copper thickness, trace width, dielectric thickness and constants, it is critical that these factors be controlled and verified by the fabricator. It is also critical that these factors be designed into a standard medium that will allow for integrity testing of the controlled impedance circuitry prior to high-volume production.


It is a common practice to perform TDR testing of controlled impedance boards, usually required as the acceptance criterion by the customer. Viasystems utilizes a 1% AQL sample plan. Any failures from this plan will generate a 100% test requirement.

With any testing requirement there will be difficulty in accessing the controlled impedance trace for verification.
There may be an option of adding test pads on the board, but this may affect the performance of the trace and occupy valuable routing space. Separation within the plane layers or split planes can raise issues with the accuracy of the impedance testing. Actual PCB traces are typically shorter and include branches to circuitry and to vias between layers.
This can affect the integrity of testing impedance-controlled traces within the actual circuitry of the board.

With these factors affecting the measurement accuracy of the actual circuitry, it is common practice for the PCB manufacturer to generate impedance test coupons. These coupons represent the circuitry designed within the board, but are controlled to known trace lengths, which the impedance formulas are generated from.
The test coupons are typically small PCB’s with trace lengths at a minimum of 152.4mm (six inches). The coupons are processed under the same controls as the main PCB. The TDR testing is then performed on the coupon and the impedance data can be correlated back to the feature size and processing parameters.


Another option used by some designers on very large board images is to incorporate a test coupon or test traces internal to the board image. It is imperative that these internal coupons or test traces adhere to the test coupon description below. This is to ensure ease of testing and result in accurate measurements.





The impedance test coupons are actually small PCBs on the same manufacturing panel as the main board itself. They are typically one inch wide by eight inches in length (depending on the number of layers requiring TDR testing in the design) and include traces of the same width and copper weight as the main PCB. The hole size and patterns are critical to ensure accurate testing with standard SMA probe heads used by most TDR manufacturers. See Figure 1.

See .pdf file for full article with illustrations. 

The coupon will be located on the manufacturing panel in a position to best represent board conditions for etching, plating, lamination, and surface finishes. The coupon is also positioned on the panel to best represent consistency across the entire manufacturing panel. When the artwork data is generated for the controlled impedance traces, the same aperture or ‘D’ codes used on the main board are also used on the coupon. See Figure 2.

See .pdf file for full article with illustrations. 



This cross-section diagram demonstrates an impedance test coupon for a board with two surface microstrip traces and two internal stripline traces. The reference planes are interconnected with plated through hole vias.  

The two surface microstrip traces are formed on layers 1 and 8, with reference planes on layers 2 and 5 respectively. The two stripline layers are formed on layers 3 and 6 with reference planes on layers 2 and 4, along with reference plane layers 5 and 7 respectively. See Figure 3.

See .pdf file for full article with illustrations.                                                                                                                      

Have more questions? Submit a request


Please sign in to leave a comment.
Powered by Zendesk